1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices, especially very large scale integration (VLSI) devices. More particularly, it relates to a method and apparatus for patterning workpieces for producing such devices with a high degree of accuracy.
2. Description of the Prior Art
Recent research and development in semiconductor devices has concentrated on a higher degree of miniaturization and higher packaging densities. Such miniaturization and high density packaging of patterns can be realized by compound techniques such as patterning resists and etching the surfaces of the semiconductor substrates, and using the patterned resists as masks.
Among these techniques, patterning can be achieved very precisely, i.e., to a limit of less than 0.2 .mu.m, by employing an electron beam exposure system now in practical use. This electron beam exposure system has the following advantages. First, very precise patterning can be obtained with a minimum line width of about 0.1 .mu.m, giving a higher resolution than that of light. Second, since it is possible to establish a very high positioning accuracy when a step and repeat method is used, each two adjacent subpatterns and each two adjacent strips can be finely aligned with each other. Third, because of the above second advantage, a plurality of subpatterns can be accurately set up to obtain a considerably large size pattern. Fourth, the input data for defining each pattern can be easily adapted to computer processing. Fifth, the number of steps can be reduced below those needed in a light exposure system, thus minimizing the time required for making each device. Further, the electron beam exposure system itself can also work as a pattern generating system.
Note, in view of the above advantages, the electron beam exposure system is used during the manufacture of the devices for dealing with a variety of workpieces, such as a reticle, a master mask, a wafer, and the like. The workpiece is usually supported at three or more points on the bottom thereof, to maintain the workpiece in a position which is horizontal relative to the incident electron beam. In practice, however, this horizontal relation cannot be strictly maintained. This is because the surface of the work piece is slightly deformed, i.e., is not truly flat due to its own weight. The areas of the surface just above the supporting points can maintain the desired height, but areas apart from the supporting points necessarily drop to a level lower than that desired. Thus, elastic deformation by compression and/or elastic deformation by tension are created on the surface of the workpiece to be patterned by the electron beam. Such elastic deformations result in pattern pitch errors, and thereby, produce undesirable pattern distortion.
The pitch errors may be caused by elastic deformation of the workpiece, nontrue flatness of the surface on which the workpiece is supported at the points, and nonuniformity of the thickness of the workpiece. Conventionally, small pitch errors, i.e., smaller than about 0.5 .mu.m, cause little or no problem, and therefore, such small pitch errors are disregarded. However, in VLSI devices, even pitch errors of about 0.5 .mu.m cannot be permitted, and a higher positioning accuracy is demanded in order to attain a further miniaturization and a denser packaging of the integrated circuit (IC) patterns. Accordingly, the permissible error for positioning accuracy now becomes very limited and, for example, a pitch error of about 0.1 .mu.m, at least, must be satisfied.
Among the above-mentioned causes of pitch errors, the present invention refers mainly to the elastic deformation of the workpiece. The remaining factors, i.e., the flatness and uniformity of thickness of the workpiece, may be easily improved by known techniques.